Modelling

Publications

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Converting from Distributed to Lumped Elements

For more information see:

• P. Davidge and A.P. Freundorfer, "Converting from Distributed to Lumped Elements,," ISSCS2013 International Symposium on Systems and Circuits, Iasi Romania, July 9- July 12, 2013, P94, pp. 1- 4.

Extracting Parasitics in Basic Electronic Components

Filter Photo

Using Ideal filter cpomponent values.

Taking into consideration parasitics

For more information see:

• A.P. Freundorfer and A. Alappat, "A Study in Extracting Parasitics in Basic Electronic Components,," ISSCS2011 International Symposium on Systems and Circuits, Iasi Romania, June 30- July 1, 2011, Digital Object Identifier: 10.1109/ISSCS.2011.5978737, pp. 1- 4

Lumped Element Circuit Modelling in Presence of Substrate-Through-Via

A. P. Freundorfer and Y. Jamani*
Department of Electrical and Computer Engineering
Queen's University
Kingston, Ontario, CANADA K7L 3N6

*Canadian Microelectronics Corporation
210A Carruthers Hall
Kingston, Ontario, Canada K7L 3N6

Abstract-Commercial use of LMDS will require a very low cost solution for making components in the Ka-band. To do this, an inexpensive device technology is necessary with a high level of integration. A lumped element design methodology is present that utilizes EM simulation to yeild accurate and predictable results.

EM sim Layout

Chip photo

Simulation: Hspice, HP/eesof Libra series IV and Zeland IE3D
Layout tools: HP/eesof Libra series IV (secondary), Zeland IE3D (primary) and Cadence (secondary)
Fab: Nortel HBT
Technical Support: CRC and Nortel Technologies
Funding: NSERC and Nortel Technologies

For more information see:

• A.P. Freundorfer and Y. Jamani, "Lumped Element Circuit Modelling in the Presence of Substrate-Through-Via," Symposium on Antenna Technology and Applied Electromagnetics, ANTEM'98, Ottawa, Canada, Aug. 1998, pp. 155-158.

Noise Characteristics of GaInP/GaAs HBT at 29 GHz

B. Lemna and A.P. Freundorfer
Department of Electrical and Computer Engineering
Royal Military College of Canada
Kingston, Ontario, Canada
freund@eleceng.ee.queensu.ca

Abstract-A characterization of bias and emitter periphery-to-area ratio (Pe/Ae) of GaInP/GaAs HBT at 29 GHz is presented. The measured data of f_max, f_t, F_min, associated gain (G_a) and noise measure (NM) for four transistors were obtained. It is shown that the larger periphery-to-area ratio of the emitter, Pe/Ae, the lower the F_min with a minimum. The best transistor, an array of twenty 2x2 mm², had F_min=2.81 dB, G_a = 4.9dB and NM=1.35.

Transistor test structures

Simulation: Hspice
Layout tools: Cadence
Fab: Nortel HBT
Technical Support: CRC and Nortel Technologies
Funding: NSERC and Nortel Technologies

For more information see:

• B. Lemna and A.P. Freundorfer, "Noise Characteristics of GaInP/GaAs HBT at 29 GHz," Symposium on Antenna Technology and Applied Electromagnetics, ANTEM'98, Ottawa, Canada, Aug. 1998, pp. 57-60.

• B. Lemna, " Optimal Size and Geometry for Low Noise HBT," Royal Military College, M.Sc. 1997.

Interconnect Modelling of Coplanar HBT Transistor Arrays

A. P. Freundorfer and Y. Jamani*
Department of Electrical and Computer Engineering
Queen's University
Kingston, Ontario, CANADA K7L-3N6 

*Canadian Microelectronics Corporation
210A Carruthers Hall
Kingston, Ontario, Canada K7L 3N6

Abstract-A method of modelling common-emitter and common-base transistor arrays using transmission line theory is presented. A comparison between measured results and simulation shows that modelling the interconnect between transistors in the array is good up to 40 GHz.

Layout of an array of 2x10 transistors with emitter array of 2x2 mm. The transistor is in a cascode configuration.